/*
 * @ : Copyright (c) 2021 Phytium Information Technology, Inc. 
 *  
 * SPDX-License-Identifier: Apache-2.0.
 * 
 * @Date: 2021-08-23 16:25:25
 * @LastEditTime: 2021-08-26 11:25:45
 * @Description:  This files is for 
 * 
 * @Modify History: 
 *  Ver   Who        Date         Changes
 * ----- ------     --------    --------------------------------------
 */
#ifndef BSP_DRIVERS_ETH_F_GMAC_PHY_H
#define BSP_DRIVERS_ETH_F_GMAC_PHY_H

#ifdef __cplusplus
extern "C"
{
#endif

#include "kernel.h"
#include "gmac.h"

#define PHY_MAX_NUM                         (32)
#define PHY_DELAY_US                        (100)

/* Generic MII registers. */
#define PHY_MII_CTRL_REG		            0x00	/* Basic mode control register */
#define PHY_MII_STATUS_REG		            0x01	/* Basic mode status register  */
#define PHY_MII_PHYSID1_REG		            0x02	/* PHYS ID 1                   */
#define PHY_MII_PHYSID2_REG		            0x03	/* PHYS ID 2                   */
#define PHY_MII_AUTONEG_REG	                0x04	/* Advertisement control reg   */
#define PHY_MII_LP_REG                      0x05	/* Link partner ability reg    */
#define PHY_MII_AUTONEG_EX_REG	            0x06	/* Expansion register          */
#define PHY_MII_NEXT_PAGE_REG               0x07    /* Next Page Transmit Register */
#define PHY_MII_LP_NEXT_PAGE_REG            0x08    /* Link Partner Next Page Register */
#define PHY_MII_CTRL1000_REG	            0x09	/* 1000BASE-T control          */
#define PHY_MII_STAT1000_REG	            0x0a	/* 1000BASE-T status           */
#define PHY_MII_MMD_CTRL_REG	            0x0d	/* MMD Access Control Register */
#define PHY_MII_MMD_DATA_REG	            0x0e	/* MMD Access Data Register */
#define PHY_MII_ESTATUS_REG		            0x0f	/* Extended Status             */
#define PHY_MII_DCOUNTER_REG	            0x12	/* Disconnect counter          */
#define PHY_MII_FCSCOUNTER_REG	            0x13	/* False carrier counter       */
#define PHY_MII_NWAYTEST_REG	            0x14	/* N-way auto-neg test reg     */
#define PHY_MII_RERRCOUNTER_REG	            0x15	/* Receive error counter       */
#define PHY_MII_SREVISION_REG	            0x16	/* Silicon revision            */
#define PHY_MII_RESV1_REG		            0x17	/* Reserved...                 */
#define PHY_MII_LBRERROR_REG	            0x18	/* Lpback, rx, bypass error    */
#define PHY_MII_PHYADDR_REG		            0x19	/* PHY address                 */
#define PHY_MII_RESV2_REG		            0x1a	/* Reserved...                 */
#define PHY_MII_TPISTATUS_REG	            0x1b	/* TPI status for 10mbps       */
#define PHY_MII_NCONFIG_REG		            0x1c	/* Network interface config    */

/* Common PHY Registers (AR8035) */
#define PHY_INTERRUPT_ENABLE_OFFSET ((u16)0x12)
#define PHY_INTERRUPT_ENABLE_LINK_FAIL 0x00000800U              /* Link fail interrupt, 0  Interrupt disable , 1 Interrupt enable */

/* Basic mode control register */
#define PHY_MII_CR_RES                      GENMASK(5, 0) /* Unused...                   */
#define PHY_MII_CR_SPEED_SEL_MSB            BIT(6) /* MSB of Speed (1000)         */
#define PHY_MII_CR_COLLISION_TEST           BIT(7) /* Collision test              */
#define PHY_MII_CR_DUPLEX_MODE              BIT(8) /* Full duplex                 */
#define PHY_MII_CR_RESTART_AUTO_NEGO        BIT(9) /* Auto negotiation restart    */
#define PHY_MII_CR_ISOLATE                  BIT(10) /* Isolate data paths from MII */
#define PHY_MII_CR_POWER_DOWN               BIT(11) /* Enable low power state      */
#define PHY_MII_CR_AUTO_NEGOT               BIT(12) /* Enable auto negotiation     */
#define PHY_MII_CR_SPEED_SEL_LSB            BIT(13) /* Select 100Mbps              */
#define PHY_MII_CR_LOOPBACK                 BIT(14) /* TXD loopback bits           */
#define PHY_MII_CR_RESET                    BIT(15) /* Reset to default state      */

#define PHY_MII_CR_FULLDUPLEX_1000M ((u16)0x2140U)        /* Set the full-duplex mode at 1000 Mb/s */
#define PHY_MII_CR_HALFDUPLEX_1000M ((u16)0x2040U)        /* Set the half-duplex mode at 1000 Mb/s */
#define PHY_MII_CR_FULLDUPLEX_100M ((u16)0x2100U)         /* Set the full-duplex mode at 100 Mb/s */
#define PHY_MII_CR_HALFDUPLEX_100M ((u16)0x2000U)         /* Set the half-duplex mode at 100 Mb/s */
#define PHY_MII_CR_FULLDUPLEX_10M ((u16)0x0100U)          /* Set the full-duplex mode at 10 Mb/s  */
#define PHY_MII_CR_HALFDUPLEX_10M ((u16)0x0000U)          /* Set the half-duplex mode at 10 Mb/s  */

/* Basic mode status register. */
#define PHY_MII_SR_EXT_CAP                  BIT(0)  /* Ext-reg capability          */
#define PHY_MII_SR_JCD                      BIT(1)  /* Jabber detected             */
#define PHY_MII_SR_LSTATUS                  BIT(2)  /* Link status                 */
#define PHY_MII_SR_AUTO_NEGOT               BIT(3)  /* Able to do auto-negotiation */
#define PHY_MII_SR_REMOTE_FAULT             BIT(4)  /* Remote fault detected       */
#define PHY_MII_SR_AUTO_NEGOT_COMPLETE      BIT(5)  /* Auto-negotiation complete   */
#define PHY_MII_SR_MF_PREAM                 BIT(6)  /* MF Preamble Suppression */
#define PHY_MII_SR_EXT_STATUS               BIT(8)  /* Extended Status in R15 */
#define PHY_MII_SR_100HALF2		            BIT(9)	/* Can do 100BASE-T2 HDX       */
#define PHY_MII_SR_100FULL2		            BIT(10)	/* Can do 100BASE-T2 FDX       */
#define PHY_MII_SR_10HALF		            BIT(11)	/* Can do 10mbps, half-duplex  */
#define PHY_MII_SR_10FULL		            BIT(12)	/* Can do 10mbps, full-duplex  */
#define PHY_MII_SR_100HALF		            BIT(13)	/* Can do 100mbps, half-duplex */
#define PHY_MII_SR_100FULL		            BIT(14)	/* Can do 100mbps, full-duplex */
#define PHY_MII_SR_100BASE4		            BIT(15)	/* Can do 100mbps, 4k packets  */

/* MII_STAT1000 masks */
#define PHY_MII_1000BTSR_MSCF	            BIT(15) /* Master/Slave Configuration Fault */
#define PHY_MII_1000BTSR_MSCR	            BIT(14) /* Master/Slave Configuration Resolution */
#define PHY_MII_1000BTSR_LRS	            BIT(13) /* Local Receiver Status */
#define PHY_MII_1000BTSR_RRS	            BIT(12) /* Remote Receiver Status */
#define PHY_MII_1000BTSR_1000FD             BIT(11) /* Full Duplex Capability */
#define PHY_MII_1000BTSR_1000HD             BIT(10) /* Half Duplex Capability */
#define PHY_MII_1000BTSR_IDLE_ERR_CNT       GENMASK(7, 0) /* MSB of Idle Error Counter */

/* Link partner ability register. */
#define PHY_MII_LPA_SELECT                  GENMASK(4, 0) /* Selector Field */
#define PHY_MII_LPA_10HALF                  BIT(5) /* 10BASE-T half-duplex capable */
#define PHY_MII_LPA_10FULL                  BIT(6) /* 10BASE-T full-duplex capable */
#define PHY_MII_LPA_1000TXHALF              BIT(7) /* 100BASE-TX half-duplex capable */
#define PHY_MII_LPA_1000TXFULL              BIT(8) /* 100BASE-TX full-duplex capable */ 
#define PHY_MII_LPA_T4                      BIT(9) /* 100BASE-T4 capable */
#define PHY_MII_LPA_PAUSE                   BIT(10) /* capable of pause operation */
#define PHY_MII_LPA_ASY_PAUSE               BIT(11) /* asymmetric pause */
#define PHY_MII_LPA_REMOTE_FAULT            BIT(13) /* Remote Fault */
#define PHY_MII_LPA_ACK                     BIT(14) /* Acknowledge */
#define PHY_MII_LPA_NEXT_PAGE               BIT(15) /* capable of next page */

/* Expansion register for auto-negotiation. */
#define PHY_MII_ESTATUS_1000_XFULL	        BIT(15)	/* Can do 1000BX Full */
#define PHY_MII_ESTATUS_1000_XHALF	        BIT(14)	/* Can do 1000BX Half */
#define PHY_MII_ESTATUS_1000_TFULL	        BIT(13)	/* Can do 1000BT Full          */
#define PHY_MII_ESTATUS_1000_THALF	        BIT(12)	/* Can do 1000BT Half          */
#define PHY_MII_ESTATUS_MASK     (PHY_MII_ESTATUS_1000_XFULL | PHY_MII_ESTATUS_1000_XHALF | \
                                  PHY_MII_ESTATUS_1000_TFULL | PHY_MII_ESTATUS_1000_THALF)           
#define PHY_MII_ESTATUS_FULL_MASK  (PHY_MII_ESTATUS_1000_XFULL | PHY_MII_ESTATUS_1000_TFULL)


u32 GmacPhyGetAddr(GmacCtrl *pCtrl);
u32 GmacPhyReadReg(GmacCtrl *pCtrl, u16 phyReg, u32 *pRegVal);
u32 GmacPhyWriteReg(GmacCtrl *pCtrl, u16 phyReg, u32 regVal);

#ifdef __cplusplus
}
#endif

#endif // !